1. Field of the Invention
The present invention relates to a semiconductor package and a fabrication method thereof.
2. Background of the Related Art
A multi-layer substrate can be used for semiconductor packages, such as a PPGA PKG (plastic Pin Grid Assay Package), a PBGA PKG (Plastic Ball Grid Array Package), a PLGA PKG (Plastic Pin Land Grid Array Package), or the like. The multi-layer substrate is often formed such that a substrate with a certain circuit pattern is insulatedly laminated to multiple layers and the laminated substrates are electrically connected between circuit patterns of each substrate by a through hole.
For example, a method for fabricating a laminated multi-layer substrate to fabricate a semiconductor package is disclosed in Japanese Patent Publication No. 10-223800 (U.S. Pat. No. 6,074,567). In this method, an inner circuit board having an opening is formed at a central portion and a bonding portion is formed adjacent to the opening to attach a gold wire connected to a semiconductor chip. After a cavity is formed by the opening by staking the inner circuit boards, an outer circuit board is laminated at an outermost layer to seal the cavity of the laminated inner circuit board.
Thereafter, a through bore is formed in the laminated body, which is fabricated as described above, an electroless-plated copper coating film and an electrolysis-plated copper coating film are formed at an inner side of the through bore, and a first plate nickel coating film is formed. At this time, since the bonding portion of the inner circuit board is covered with the outer circuit board, plating is not made thereon.
In this state, a circuit pattern forming process is performed by etching the laminated body, then coating a solder resist (S/R) thereon. Next, a certain portion of the outer circuit board corresponding to the opening of the inner circuit board is removed by a device, such as a router, to expose the cavity and the bonding portion. Finally, a plated nickel/gold coating film is formed at the bonding portion and at the through bore, thereby forming a through hole.
However, such a fabrication method makes it difficult to mechanically process. Additionally, previously formed circuit patterns are often damaged in this process due to impacts or other effects occurring during the process. Also, the plated nickel/gold coating layer is unnecessarily formed at the through hole.
In an effort to solve such problems, a second method has been tried. First, each substrate is laminated to form a cavity by upwardly opening the semiconductor package with an organic substance filled inside the cavity. Next, a through hole is formed, patterning is performed thereon, and the organic substance is removed. Finally, the lowermost substrate is processed, whereby the through hole is formed while bonding pads inside the cavity are protected.
However, also in this method, the lowermost substrate is subjected to processing and this method does not completely remove the organic substances filled in the cavity. Thus, since the organic substrates remaining in the cavity works as a foreign material when the nickel/gold coating layer is formed at the bonding portion, it deteriorates the quality of a semiconductor package.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
To achieve at least the above objects in whole or in parts and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for fabricating a semiconductor package including forming a plurality of patterns formed plates, wherein each pattern formed plate is formed by forming first plated copper layers on upper and lower surfaces of an insulation substrate, forming a pattern in the first plated copper layers formed at upper and lower surfaces of the insulation substrate, and forming an opening by removing a central portion of the insulation substrate with the first plated copper pattern formed thereon, forming a bonding pad pattern around the opening of at least one of the pattern formed plates, and forming a first coating layer with a non-copper metal material on the bonding pad pattern, forming a laminated body by laminating the plurality of pattern formed plates to each other, forming a second plated copper layer by forming a through bore in the laminated body and forming a second copper plating on the through bore and the first coating layer, and forming a bonding pad by removing the second plated copper layer formed on the first coating layer, and forming a second coating layer with a non-copper metal material on the first coating layer.
To further achieve at least the above objects in whole or in parts and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for fabricating a semiconductor package, including forming a plated copper pattern formed plate by forming a first plated copper layer on upper and lower surfaces of a first insulation substrate, forming a pattern on first plated copper formed at the upper and lower surfaces of the first insulation substrate, and forming an opening by removing a central portion of the first insulation substrate with the first plated copper pattern formed thereon, forming an inner circuit pattern formed plate by forming a second plated copper pattern on an upper surface or a lower surface of a second insulation substrate, forming a third plated copper layer on a second plated copper, and forming an opening by removing a central portion of the second insulation substrate with the second plated copper pattern and the third plated copper formed thereon, forming a lower circuit pattern formed by forming a fourth plated copper pattern on an upper surface or a lower surface of a third insulation substrate, forming a fifth plated copper layer on the fourth plated copper, forming an opening by removing a central portion of the third insulation substrate with the fourth plated copper pattern and the fifth plated copper formed thereon, forming a bonding pad by forming a first nickel/gold plating layer around the opening of the inner circuit pattern formed plate and the lower circuit pattern formed plate, forming a laminated body by laminating the plated copper pattern formed plate onto the inner circuit pattern formed plate and the inner circuit pattern formed plate onto the lower circuit pattern formed plate using bonding sheets and sequentially attaching the formed plates, forming a through bore in the laminated body, forming a sixth plated copper layer on an inner circumferential surface of the through bore, the surface of the laminated body and the first nickel/gold plating layer, removing the sixth plated copper layer formed on the first nickel/gold plating layer of the laminated body, forming an outer circuit pattern by patterning a plated copper formed with the sixth plated copper layer formed thereon, and forming a second nickel/gold plating layer on the first nickel/gold plating layer of the laminated body and at a predetermined portion of the outer circuit pattern formed at an upper surface of the laminated body to form a bonding pad and a ball pad, respectively.
To further achieve at least the above objects in whole or in parts and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for fabricating a semiconductor package, including forming a plurality of circuit patterns, forming a cavity in a central portion of each of the plurality of circuit patterns, mounting a semiconductor chip within the cavity, and forming a bonding pad circuit pattern to be connected to the semiconductor within the cavity, wherein a first coating layer is formed with a non-copper metal material at the bonding pad circuit pattern and a copper plating is formed on the first coating layer.
To further achieve at least the above objects in whole or in parts and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for fabricating a semiconductor package, including forming a plurality of patterns formed plates, wherein each pattern formed plate is formed by forming first plated copper layers on upper and lower surfaces of an insulation substrate, forming a pattern in the first plated copper layers formed at upper and lower surfaces of the insulation substrate, and forming an opening by removing a central portion of the insulation substrate with the first plated copper pattern formed thereon, forming a bonding pad pattern around the opening of at least one of the pattern formed plates, forming a first coating layer with a non-copper metal material on the bonding pad pattern, forming a laminated body by laminating the plurality of pattern formed plates to one another, wherein the openings of the plurality of patterns formed plates are aligned to form a cavity, forming a through bore through the laminated body, forming a second plated copper layer on the through bore and the first coating layer, removing the second plated copper layer formed on the first coating layer, forming a second coating layer with a non-copper metal material on the first coating layer, thereby forming a bonding pad, mounting a semiconductor chip in the cavity, connecting the semiconductor chip and the bonding pad by a connection line, and filling the cavity with a filler.
To further achieve at least the above objects in whole or in parts and in accordance with the purpose of the invention, as embodied and broadly described herein, a method of forming a semiconductor package, including forming a plurality of plates, wherein each plate is formed by coating a first coating on a substrate, and forming an opening in a central portion of the substrate with the first coating thereon, forming a bonding pad pattern on at least one of the plurality of plates, wherein a second coating is coated onto the bonding pad pattern, forming a body by stacking the plurality of plates, forming a through bore in the body, and coating the through bore with a third coating.
To further achieve at least the above objects in whole or in parts and in accordance with the purpose of the invention, as embodied and broadly described herein, a semiconductor package, including a laminated body, including a plurality of plates laminated into a body, wherein each plate comprises a substrate, a first coating and an opening, a bonding pad on at least one of the plurality of plates, wherein the bonding pad comprises a metal layer, and a through bore in the laminated body with a second coating therein, a heat sink attached to a lower surface of the laminated body, a semiconductor chip on an upper surface of the heat sink in the openings of the plurality of plates, and a connector for connecting the semiconductor chip to the laminated body, wherein the connector is connected to the bonding pad of the laminated body.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.